Mike Clark discusses the Zen 6 architecture at AMD’s In‑Depth event, emphasizing the dense core’s 4 MB L3 cache per core.
AMD UNVEILS ZEN 6 AND ZEN 6C: HIGH‑FREQUENCY CORE, AI FOCUS
*AMD’s latest Zen 6 family pushes frequency, L3 cache and AI vector support. Mike Clark, the original Zen architect, explains why the dense core is now the flagship and how Zen 6c balances power and performance.*
AMD’s Mike Clark, the original architect of the Zen microarchitecture, sat down at the company’s In‑Depth event to detail the upcoming Zen 6 family. The conversation revealed a clear shift: the dense core, once a niche density play, is now the flagship performance engine. Clark emphasized that the new high‑frequency design packs a full 4 MB L3 cache per core, scaling to 32 cores and 128 MB of L3 on a single die. At the same time, AMD introduced Zen 6c, a lower‑frequency sibling that expands internal queues to preserve IPC without demanding higher clocks. The interview also covered AI‑focused vector upgrades and a deliberate reduction in integer multiply units, underscoring AMD’s intent to balance raw speed with efficiency.
What differentiates Zen 6 from Zen 5?
Zen 6 builds on the dual‑decode front end introduced in Zen 5, but AMD re‑engineered the fetch and decode pipelines for tighter power‑to‑performance ratios. The new design reduces wasted power while delivering more efficient instruction delivery. A unified scheduler from Zen 5 gave way to distributed schedulers that feed the ALUs directly, allowing AMD to drop a third integer multiply unit without hurting throughput. The result is a cleaner, more area‑efficient core that still leverages the two‑block fetch capability of Zen 5.
Why AMD added Zen 6c and how it differs
Zen 6c targets lower frequency envelopes while keeping the same software model as the high‑frequency Zen 6. Because it does not chase the top clock, the core can afford larger queues, including a bigger floating‑point scheduler. The vector scheduler also grew, giving Zen 6c extra capacity to pull more IPC in an SMT environment. AMD’s goal was to avoid a software delta between the two variants, ensuring developers can use the same optimizations across both.
AI and vector enhancements in Zen 6
AMD added two VNNI units late in the design to strengthen AI inference handling. While the core will never replace a GPU, the extra VNNI pipes improve orchestration of smaller models. On the vector side, Zen 6 can now issue four vector loads of 128 or 256 bits, a step up from Zen 5’s two‑load limit. The architecture already supports two 512‑bit loads, giving a total of 1,024 wires to the load unit, and the new load capability leverages that existing bandwidth.
Design trade‑offs: multiplier units and scheduler changes
Zen 6 reduces integer multiply units from three to two, a decision rooted in Zen 5’s experience with a unified scheduler that showed little performance gain from the extra multiplier. By simplifying the scheduler and cutting the multiplier count, AMD saves die area and power. The dense version of Zen 6 also features a full 4 MB L3 cache per core, scaling to 32 cores and 128 MB of L3 across the chip, positioning it as the top‑of‑the‑line performance core in the family.
Frequently asked questions
How many cores and how much L3 cache does the Zen 6 dense core have?
Zen 6’s dense core features 32 cores with a full 4 MB L3 cache per core, totaling 128 MB of L3.
What changes were made to integer multiply units in Zen 6?
The design reduced integer multiply units from three to two to simplify the scheduler and save area.
Why did AMD add extra VNNI units to Zen 6?
AMD added two VNNI units late in the design to improve AI inference handling, aligning the core with growing AI workload demands.
Zen 6 and Zen 6c signal AMD’s dual‑track strategy: a bleeding‑edge, high‑frequency core for raw performance and a power‑conscious sibling that keeps software compatibility intact. By tightening the scheduler, adding AI‑oriented VNNI units and expanding vector load capacity, AMD positions the Zen 6 family to meet both data‑center and edge workloads. The next silicon rollout will test whether these architectural bets translate into measurable gains in real‑world applications.
Sources: Hacker News article "Talking Zen 6 with Mike Clark at AMD In-Depth"